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Native AB transport: bench-controller proof of writes + PCCC, then decide libplctag deletion #592

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opened 2026-10-08 02:31:08 -04:00 by dohertj2 · 5 comments
dohertj2 commented 2026-10-08 02:31:08 -04:00
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The T21 real-press gate was read-only; every native write and every AbLegacy native path is proven only against ab_server. Design P6 (delete libplctag) is blocked on a bench controller. Hardware-only residuals left by closed #566/#567/#572/#582.
Sources: docs/drivers/AbCip.md (Known gaps), docs/drivers/AbLegacy.md §Wire evidence, docs/plans/2026-10-07-native-ab-transport-design.md §8 (P6), §9.

  • AbCip native writes on a CompactLogix/Micro800, incl. wide-struct fragmented WRITE (#567)
  • Mixed STRING/array MSP reply packing on a real controller (#582)
  • Which CIP status a real Logix returns on target-side connection close (0x0107/0x0203) vs dropping TCP (#566)
  • Whether a real controller ever lists instances out of order (#572); logixpccc SLC framing; routed paths beyond 1,0
  • AbLegacy native on an SLC/MicroLogix: S:0 probe, B/T/C/R/S/L/ST/A/O/I files, T/C/R sub-element offsets, ST byte order, F8 write
  • ab_server bit-file write gap (B3:0/5): current fixture proof recorded 2026-10-09 in docs/plans/2026-10-07-native-ab-transport-gate-results.md. SLC500/MicroLogix both transports pass neighbor-preserving word RMW; libplctag PLC-5 passes, native PLC-5 intentionally refuses (#571). Original cause undetermined; no patch needed. This is simulator evidence, not physical-controller proof.
  • With that evidence, decide P6 (remove the libplctag package + adapters)

Filed 2026-10-08 by the pending/deferred-work sweep after the #562–#591 issue sweep.

The T21 real-press gate was read-only; every native write and every AbLegacy native path is proven only against `ab_server`. Design P6 (delete libplctag) is blocked on a bench controller. Hardware-only residuals left by closed #566/#567/#572/#582. Sources: docs/drivers/AbCip.md (Known gaps), docs/drivers/AbLegacy.md §Wire evidence, docs/plans/2026-10-07-native-ab-transport-design.md §8 (P6), §9. - [ ] AbCip native writes on a CompactLogix/Micro800, incl. wide-struct fragmented WRITE (#567) - [ ] Mixed STRING/array MSP reply packing on a real controller (#582) - [ ] Which CIP status a real Logix returns on target-side connection close (0x0107/0x0203) vs dropping TCP (#566) - [ ] Whether a real controller ever lists instances out of order (#572); `logixpccc` SLC framing; routed paths beyond `1,0` - [ ] AbLegacy native on an SLC/MicroLogix: `S:0` probe, B/T/C/R/S/L/ST/A/O/I files, T/C/R sub-element offsets, ST byte order, F8 write - [x] ab_server bit-file write gap (`B3:0/5`): current fixture proof recorded 2026-10-09 in docs/plans/2026-10-07-native-ab-transport-gate-results.md. SLC500/MicroLogix both transports pass neighbor-preserving word RMW; libplctag PLC-5 passes, native PLC-5 intentionally refuses (#571). Original cause undetermined; no patch needed. This is simulator evidence, not physical-controller proof. - [ ] With that evidence, decide P6 (remove the libplctag package + adapters) _Filed 2026-10-08 by the pending/deferred-work sweep after the #562–#591 issue sweep._
dohertj2 added the driver/abcipdriver/ablegacy labels 2026-10-08 02:31:08 -04:00
dohertj2 commented 2026-10-08 18:52:11 -04:00
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From #636: driver-gaps item #248 (AbLegacy PD/MG/PLS/BT file types) is tracked here. From #634: items #242/#243 (AbCip) are also tracked here.

From #636: driver-gaps item #248 (AbLegacy PD/MG/PLS/BT file types) is tracked here. From #634: items #242/#243 (AbCip) are also tracked here.
dohertj2 commented 2026-10-09 04:55:26 -04:00
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Progress 2026-10-09 (master 12aa293c, pushed). Evidence: docs/plans/2026-10-07-native-ab-transport-gate-results.md (sections "hw4 evidence batch" and "#611 UDT member-write gate").

Done:

  • AbCip native writes on a real CompactLogix (Z35162, user-approved one-offs, all restored): scalars DINT test2, BOOL Program:UN01_Press.xxtest, REAL Program:ES03_EM03_Zone3._ff_test; UDT members _EmptyTemperatureSegment.ID/.Enable(BIT)/.HoldTime. Tags chosen from an L5X census (no routine/alias/trend reference, not in the Galaxy map).
  • #582 mixed STRING/array MSP (read-only): STRING + array element + DINT[32] + 2 scalars rode one Multiple Service Packet in 5/5 attempts; values equal bracketing single reads.
  • #572 listing order (read-only): 3162 tags over 41 pages, none non-ascending (instance ids skip, but ascend).
  • ab_server bit-file write gap (B3:0/5 → 0x803D0000, May 2026, libplctag + SLC500): does not reproduce any more; AbLegacyBitWriteTests sets/clears bits and asserts the whole word (neighbours preserved) on SLC500 + MicroLogix (both transports) and PLC-5 libplctag. Original cause undetermined. PLC-5 native returns the same code for the unrelated #571 refusal.

Still open (hardware):

  • #567 fragmented wide-struct WRITE (no safe large unreferenced struct on the press)
  • array / STRING native writes on hardware
  • #566 CIP status on target-side connection close (needs a long idle session on a production press — not approved)
  • logixpccc SLC framing; routed paths beyond 1,0
  • AbLegacy native on an SLC/MicroLogix (all items in the body)
  • From #611: ALMA/ALMD projection on a real controller (Z35162 has none); sibling-bit preservation within one hidden host SINT; libplctag member-write path on hardware
  • Then decide P6. Suggested split: AbCip's libplctag adapter could go once #567 + array/STRING writes have evidence; AbLegacy's must stay until PCCC hardware exists (libplctag is its default and only wire-proven path).
Progress 2026-10-09 (master `12aa293c`, pushed). Evidence: `docs/plans/2026-10-07-native-ab-transport-gate-results.md` (sections "hw4 evidence batch" and "#611 UDT member-write gate"). Done: - **AbCip native writes on a real CompactLogix** (Z35162, user-approved one-offs, all restored): scalars DINT `test2`, BOOL `Program:UN01_Press.xxtest`, REAL `Program:ES03_EM03_Zone3._ff_test`; UDT members `_EmptyTemperatureSegment.ID/.Enable(BIT)/.HoldTime`. Tags chosen from an L5X census (no routine/alias/trend reference, not in the Galaxy map). - **#582 mixed STRING/array MSP** (read-only): STRING + array element + DINT[32] + 2 scalars rode one Multiple Service Packet in 5/5 attempts; values equal bracketing single reads. - **#572 listing order** (read-only): 3162 tags over 41 pages, none non-ascending (instance ids skip, but ascend). - **ab_server bit-file write gap** (`B3:0/5` → 0x803D0000, May 2026, libplctag + SLC500): does not reproduce any more; `AbLegacyBitWriteTests` sets/clears bits and asserts the whole word (neighbours preserved) on SLC500 + MicroLogix (both transports) and PLC-5 libplctag. Original cause undetermined. PLC-5 native returns the same code for the unrelated #571 refusal. Still open (hardware): - [ ] #567 fragmented wide-struct WRITE (no safe large unreferenced struct on the press) - [ ] array / STRING native writes on hardware - [ ] #566 CIP status on target-side connection close (needs a long idle session on a production press — not approved) - [ ] `logixpccc` SLC framing; routed paths beyond `1,0` - [ ] AbLegacy native on an SLC/MicroLogix (all items in the body) - [ ] From #611: ALMA/ALMD projection on a real controller (Z35162 has none); sibling-bit preservation within one hidden host SINT; libplctag member-write path on hardware - [ ] Then decide P6. Suggested split: AbCip's libplctag adapter could go once #567 + array/STRING writes have evidence; AbLegacy's must stay until PCCC hardware exists (libplctag is its default and only wire-proven path).
dohertj2 commented 2026-10-09 05:24:02 -04:00
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AbLegacy on a real MicroLogix 1400 — 2026-10-09 (Z-33323, ab://10.201.44.231/, empty path).

Press selection: checked cycle-in-progress (N10:150/0, B3:0/4) on the reachable presses. Z-33470 was mid-cycle and was left alone. Z-33323 was idle (both false, pump input I:0/0 off, O:0 = 0) before and after the tests. The other North presses time out on TCP from the VPN.

Native reads — all Good and equal to libplctag where libplctag works: S:0 (default probe), S:57 = 1400, S:4; N; F8 (2.1, 200.0); B words and bits; T .PRE/.ACC/.DN (incl. T40); C .PRE/.ACC/.DN; R .LEN/.POS/.DN; ST "Z-33323" (byte order correct); O:0, O:0/3, I:0, I:0/0.

Native writes (restored, verified): N7:23 0→4242→0 (neighbours unchanged); F8:190 0→42.5→0; B3:200 bit RMW: set /5 → 32, set /3 → 40, clear /5 → 8, clear /3 → 0 (neighbour words unchanged). Addresses vetted against the sibling Z-33756 program export (no ladder/symbol/HMI/panel/migration reference) plus Z-33323's own symbol table, and read 0 first.

Defect found: libplctag (the AbLegacy default) fails S:/O:/I: and control status bits on this controller — including the default probe S:0 — filed as #659.

Checklist update:

  • AbLegacy native on a MicroLogix: S:0 probe, B/T/C/R/S/ST/O/I, T/C/R sub-element offsets, ST byte order, F8 write
  • L and A files (no press in the fleet has them), function files, SLC 5/05, PLC-5, logixpccc
  • #659 (libplctag S/O/I) — relevant to the P6 decision: on MicroLogix the native transport is now the better-evidenced path

Raw output: docs/plans/2026-10-07-native-ab-transport-gate-results.md (2026-10-09 MicroLogix section) and docs/drivers/AbLegacy.md §Wire evidence — on master with the next push.

**AbLegacy on a real MicroLogix 1400 — 2026-10-09** (Z-33323, `ab://10.201.44.231/`, empty path). Press selection: checked cycle-in-progress (`N10:150/0`, `B3:0/4`) on the reachable presses. Z-33470 was mid-cycle and was left alone. Z-33323 was idle (both false, pump input `I:0/0` off, `O:0` = 0) before and after the tests. The other North presses time out on TCP from the VPN. **Native reads — all Good and equal to libplctag where libplctag works:** `S:0` (default probe), `S:57` = 1400, `S:4`; N; F8 (2.1, 200.0); B words and bits; T `.PRE/.ACC/.DN` (incl. T40); C `.PRE/.ACC/.DN`; R `.LEN/.POS/.DN`; ST `"Z-33323"` (**byte order correct**); `O:0`, `O:0/3`, `I:0`, `I:0/0`. **Native writes (restored, verified):** `N7:23` 0→4242→0 (neighbours unchanged); `F8:190` 0→42.5→0; `B3:200` bit RMW: set /5 → 32, set /3 → 40, clear /5 → 8, clear /3 → 0 (neighbour words unchanged). Addresses vetted against the sibling Z-33756 program export (no ladder/symbol/HMI/panel/migration reference) plus Z-33323's own symbol table, and read 0 first. **Defect found:** libplctag (the AbLegacy default) fails `S:`/`O:`/`I:` and control status bits on this controller — including the default probe `S:0` — filed as #659. Checklist update: - [x] AbLegacy native on a MicroLogix: `S:0` probe, B/T/C/R/S/ST/O/I, T/C/R sub-element offsets, ST byte order, F8 write - [ ] L and A files (no press in the fleet has them), function files, SLC 5/05, PLC-5, `logixpccc` - [ ] #659 (libplctag S/O/I) — relevant to the P6 decision: on MicroLogix the native transport is now the *better*-evidenced path Raw output: `docs/plans/2026-10-07-native-ab-transport-gate-results.md` (2026-10-09 MicroLogix section) and `docs/drivers/AbLegacy.md` §Wire evidence — on master with the next push.
dohertj2 referenced this issue from a commit 2026-10-09 07:19:56 -04:00
Merge hw5-592 (#592)
dohertj2 commented 2026-10-09 07:20:21 -04:00
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Progress (hw5, pushed in master ea220363, merge b394413e), all on Z-35162 (CompactLogix 5069-L320ERS2, ab://10.209.70.160/1,0), user-approved one-off writes, each restored and verified:

  • #566 idle connection — answered: a real Logix drops the TCP connection after the idle connection timeout (2 s RPI × multiplier ≈ 16 s; observed close somewhere in the 16–60 s window, RST vs FIN not captured) with no CIP status. The next write fails "Broken pipe", is classed BadConnection, and the driver reconnects. Offline regression test added; AbCip.md #566 residual replaced with the observation.
  • STRING write — PASS: native write to Program:ES03_TemperatureControl._StrTmp through the production AbCipDriver, restored byte-exact.
  • Array-element write — PASS: native write to Program:EM01_PowerUnit._SEQ_EP[31] 0 → 4242 → 0; all 32 elements otherwise unchanged (the census initially missed that _SEQ_EP[1..3] are aliased sequencer step registers; element 31 is unaliased).
  • New AbCip.IntegrationTests/HardwareGate/ with a pinned (host, tag) allow-list, AB_HW_WRITE_APPROVED=1 gate, and offline guard tests; CipConnection.ForwardOpenAsync now reaches the diagnostics tap.

Still open here (need hardware / programs we don't have): #567 large-struct/fragmented writes; whole-array writes (AbCip has none by design); SLC / PLC-5 / logixpccc native; MicroLogix L/A and function files; ALMA/ALMD on real hardware; sibling-bit preservation and the libplctag UDT-member path on real hardware.

Progress (hw5, pushed in master `ea220363`, merge `b394413e`), all on Z-35162 (CompactLogix 5069-L320ERS2, `ab://10.209.70.160/1,0`), user-approved one-off writes, each restored and verified: - **#566 idle connection — answered:** a real Logix drops the TCP connection after the idle connection timeout (2 s RPI × multiplier ≈ 16 s; observed close somewhere in the 16–60 s window, RST vs FIN not captured) with no CIP status. The next write fails "Broken pipe", is classed BadConnection, and the driver reconnects. Offline regression test added; AbCip.md #566 residual replaced with the observation. - **STRING write — PASS:** native write to `Program:ES03_TemperatureControl._StrTmp` through the production AbCipDriver, restored byte-exact. - **Array-element write — PASS:** native write to `Program:EM01_PowerUnit._SEQ_EP[31]` 0 → 4242 → 0; all 32 elements otherwise unchanged (the census initially missed that `_SEQ_EP[1..3]` are aliased sequencer step registers; element 31 is unaliased). - New `AbCip.IntegrationTests/HardwareGate/` with a pinned (host, tag) allow-list, `AB_HW_WRITE_APPROVED=1` gate, and offline guard tests; `CipConnection.ForwardOpenAsync` now reaches the diagnostics tap. Still open here (need hardware / programs we don't have): #567 large-struct/fragmented writes; whole-array writes (AbCip has none by design); SLC / PLC-5 / `logixpccc` native; MicroLogix L/A and function files; ALMA/ALMD on real hardware; sibling-bit preservation and the libplctag UDT-member path on real hardware.
dohertj2 commented 2026-10-13 09:22:00 -04:00
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2026-10-13 source/documentation reconciliation (historical hardware evidence, no new live probe):

Current evidence supersedes the opening checklist. The 2026-10-09 user-approved CompactLogix gates prove scalar DINT/BOOL/REAL, UDT member, STRING and array-element native writes with restores; mixed STRING/array/scalar MSP reads match single reads; the observed target idle timeout closes TCP without a CIP status. Native MicroLogix1400 reads cover S/N/F/B/T/C/R/ST/O/I including S:0, T/C/R sub-elements and ST byte order; native N/F/B-bit writes were restored and verified. #659 fixed fallback address translation for S/O/I and unsupported control-bit names. These are recorded historical live proofs, not newly rerun gates.

The old ab_server B3:0/5 gap does not reproduce on current fixtures: AbLegacyBitWriteTests checks whole-word neighbour preservation on SLC500/MicroLogix both transports, PLC5 fallback; native PLC5 BadNotSupported is its explicit unrelated write refusal. No simulator patch is justified.

Keep open: fragmented wide-struct writes requiring a safe >MaxRequestBytes scratch value/bench target; Micro800 and routing beyond1,0; real SLC/PLC5/logixpccc native evidence; MicroLogix L/A/function files; hardware ALMA/ALMD and sibling-bit/member-write gaps. Whole-array driver writes are absent by design, so distinguish a new capability decision from a verification checkbox. P6 deletion of libplctag remains a separate scope decision after required hardware evidence.

Evidence: docs/drivers/AbCip.md:245; docs/drivers/AbLegacy.md:211; docs/plans/2026-10-07-native-ab-transport-gate-results.md:480/542/580/706/788; current #592 comments already describe progress. No immediate bounded transport implementation identified solely from this ticket; tracker reconciliation is the useful action.

2026-10-13 source/documentation reconciliation (historical hardware evidence, no new live probe): Current evidence supersedes the opening checklist. The 2026-10-09 user-approved CompactLogix gates prove scalar DINT/BOOL/REAL, UDT member, STRING and array-element native writes with restores; mixed STRING/array/scalar MSP reads match single reads; the observed target idle timeout closes TCP without a CIP status. Native MicroLogix1400 reads cover S/N/F/B/T/C/R/ST/O/I including S:0, T/C/R sub-elements and ST byte order; native N/F/B-bit writes were restored and verified. #659 fixed fallback address translation for S/O/I and unsupported control-bit names. These are recorded historical live proofs, not newly rerun gates. The old ab_server B3:0/5 gap does not reproduce on current fixtures: AbLegacyBitWriteTests checks whole-word neighbour preservation on SLC500/MicroLogix both transports, PLC5 fallback; native PLC5 BadNotSupported is its explicit unrelated write refusal. No simulator patch is justified. Keep open: fragmented wide-struct writes requiring a safe >MaxRequestBytes scratch value/bench target; Micro800 and routing beyond1,0; real SLC/PLC5/logixpccc native evidence; MicroLogix L/A/function files; hardware ALMA/ALMD and sibling-bit/member-write gaps. Whole-array driver writes are absent by design, so distinguish a new capability decision from a verification checkbox. P6 deletion of libplctag remains a separate scope decision after required hardware evidence. Evidence: docs/drivers/AbCip.md:245; docs/drivers/AbLegacy.md:211; docs/plans/2026-10-07-native-ab-transport-gate-results.md:480/542/580/706/788; current #592 comments already describe progress. No immediate bounded transport implementation identified solely from this ticket; tracker reconciliation is the useful action.
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Reference: dohertj2/lmxopcua#592
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