Phase 3 PR 51 -- DL260 X-input FC02 discrete-input mapping end-to-end test #50

dohertj2 · 2026-04-18T22:35:21-04:00

dohertj2 commented

2026-04-18 22:35:21 -04:00

Summary

Stacked on PR 50. Integration test verifying the X-input mapping (octal X-address → Modbus DI) end-to-end against the dl205.json pymodbus profile. Seeds cell 1 with value=9 so X20 octal (=DI 16) reads ON and X21 octal (=DI 17) reads OFF — proves the helper routes to the right bit AND that unpopulated X-inputs return zero rather than an exception per DL260 firmware behavior.

Uses X20 instead of X0 because X0-X15 share cell 0 with the V0 register-zero quirk marker under shared-blocks semantics; X20 lands at cell 1 which is free.

Validation

10/10 DL205 integration tests pass
No driver code changes (XInputToDiscrete helper + FC02 path landed earlier)

Test plan

X20 reads ON against seeded cell
Unpopulated X21 reads OFF cleanly (not exception)

## Summary Stacked on PR 50. Integration test verifying the X-input mapping (octal X-address → Modbus DI) end-to-end against the dl205.json pymodbus profile. Seeds cell 1 with value=9 so X20 octal (=DI 16) reads ON and X21 octal (=DI 17) reads OFF — proves the helper routes to the right bit AND that unpopulated X-inputs return zero rather than an exception per DL260 firmware behavior. Uses X20 instead of X0 because X0-X15 share cell 0 with the V0 register-zero quirk marker under shared-blocks semantics; X20 lands at cell 1 which is free. ## Validation - 10/10 DL205 integration tests pass - No driver code changes (XInputToDiscrete helper + FC02 path landed earlier) ## Test plan - [x] X20 reads ON against seeded cell - [x] Unpopulated X21 reads OFF cleanly (not exception)

dohertj2 added 1 commit 2026-04-18 22:35:22 -04:00

Phase 3 PR 51 -- DL260 X-input FC02 discrete-input mapping end-to-end test. Integration test DL205XInputTests reads FC02 at the DirectLogicAddress.XInputToDiscrete-resolved address and asserts two behaviors against the dl205.json pymodbus profile: (1) X20 octal (=decimal 16 = Modbus DI 16) reads ON, proving the helper correctly octal-parses the trailing number and adds it to the 0 base; (2) X21 octal reads OFF (not exception) -- per docs/v2/dl205.md §I/O-mapping, 'reading a non-populated X input returns zero, not an exception' on DL260, because the CPU sizes the discrete-input table to the configured I/O not the installed hardware. Pymodbus models this by returning the default 0 value for any DI bit in the configured 'di size' range that wasn't explicitly seeded, matching real DL260 behaviour. Test uses X20 rather than X0 to sidestep a shared-blocks conflict: pymodbus places FC01/FC02 bit-address 0..15 into cell 0, but cell 0 is already uint16-typed (V0 marker = 0xCAFE) per the register-zero quirk test, and shared-blocks semantics allow only one type per cell. X20 octal = DI 16 lands in cell 1 which is free, so both the V0 quirk AND the X-input quirk can coexist in one profile. dl205.json: bits cell 1 seeded value=9 (bits 0 and 3 set -> X20, X23 octal = ON), write-range extended to include cell 1 (though X-inputs are read-only; the write-range entry is required by pymodbus for ANY cell referenced in a bits section even if only reads are expected -- pymodbus validates write-access uniformly). 10/10 DL205 integration tests pass with MODBUS_SIM_PROFILE=dl205. No driver code changes -- the XInputToDiscrete helper + FC02 read path already landed in PRs 50 and 21 respectively. This PR closes the integration-test gap that docs/v2/dl205.md called out under test name DL205_Xinput_unpopulated_reads_as_zero. 9892a0253d

dohertj2 merged commit 954bf55d28 into v2

2026-04-18 22:35:26 -04:00

dohertj2 referenced this issue from a commit

2026-04-18 22:35:28 -04:00

Merge pull request 'Phase 3 PR 51 -- DL260 X-input FC02 discrete-input mapping end-to-end test' (#50) from phase-3-pr51-dl205-xinput into v2

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Reference: dohertj2/lmxopcua#50