feat(ablegacy): resolve indirect addresses at read/write time (#646)
Claude-Session: https://claude.ai/code/session_01Ef2ozxS7QPanGT8uoATbTe
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@@ -69,7 +69,7 @@ pieces for driver-side routing (e.g. deciding a bit needs read-modify-write):
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| `I:0/0` / `O:1/2` / `S:1` | Input / output / status system files (no file number) |
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| `I:017/07` | **PLC-5 only:** `I:`/`O:` word and bit indices are **octal** (#244); a digit 8/9 is a parse error |
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| `RTC:0.HR` / `HSC:0.ACC` | **MicroLogix only:** function files RTC, HSC, DLS, MMI, PTO, PWM, STI, EII, IOS, BHI (#245) |
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| `N7:[N7:0]` / `N[N7:0]:5` | Indirect (index word read from the PLC) — parsed, **not supported at runtime** (#247) |
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| `N7:[N7:0]` / `N[N7:0]:5` | Indirect (index word read from the PLC) — resolved at read/write time (#646) |
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`AbLegacyDataType` covers the corresponding PCCC types: `Bit`, `Int` (N), `Long`
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(L), `Float` (F), `AnalogInt` (A), `String` (ST), and the `TimerElement` /
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@@ -118,11 +118,18 @@ physical inputs and may reject the write.
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members default to Int32). ⚠️ **Wire-unverified on both transports:** there is no capture and no simulator
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coverage; the libplctag path passes the name through and the native transport has no file-type code for them, so
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it refuses the tag as `Unsupported` (`BadNotSupported` to the client; see Wire evidence).
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- **Indirect addressing (#247).** `N7:[N7:0]` (word from another address) and `N[N7:0]:5` (file from another
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address) parse, one level deep (the inner address must be direct, and carries the family's octal rule).
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**Runtime resolution is not implemented** (it needs a pre-read of the index word and per-resolved-address
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runtimes): reads and writes of an indirect tag answer `BadNotSupported` before any runtime is created, on both
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transports.
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- **Indirect addressing (#247 parse, #646 runtime).** `N7:[N7:0]` (word from another address) and `N[N7:0]:5` (file
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from another address) parse, one level deep (the inner address must be direct, and carries the family's octal rule).
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At runtime the driver reads the inner address first (same runtime factory, so libplctag and Native alike), requires
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an integer in range (word/element `0..255`, file `0..999`), composes the concrete address and runs the normal
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read/write path against it. **The index is re-read on every read/write - never cached** - and the previous
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resolution's handle is released when the index moves. A bad index (negative, too large, float/string source) is
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`BadOutOfRange` for that tag only (no health impact); an inner-read failure propagates its own status (a wire
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failure also degrades health like any read). **Writes** resolve then write and are **not atomic**: the index can
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change between the two PLC accesses. Bit RMW writes (`B3:[N7:0]/4`) resolve first, then RMW the concrete word.
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The Native transport never sees the bracket form (it receives the composed name), so N-file indirect stays inside
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the wire-proven envelope; other file types are as (un)verified as their direct forms. Live-gated on `ab_server`
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by `AbLegacyIndirectAddressingTests` (`N7:0=5`, `N7:5=42`, `N7:[N7:0]` reads 42).
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## Configuration
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@@ -211,7 +218,8 @@ Everything below is against the `ab_server` simulator; no real PCCC controller h
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| N-file write (`N7:5`) | capture `slc500-write-n7` + native `AbLegacyReadSmokeTests` write/read round trip (SLC 500) |
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| F-file read (`F8`) | one capture, `slc500-read-f8` (codec parity only; no native F write on a wire) |
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| S (incl. the default probe `S:0`), B, T, C, R, L, ST, A, O, I | **none** — encoded from the PCCC file-type table |
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| MicroLogix function files (RTC/HSC/...), PLC-5 octal I/O, indirect addressing | **none** — parsed only; native refuses function files and indirect names as Unsupported |
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| MicroLogix function files (RTC/HSC/...), PLC-5 octal I/O | **none** — parsed only; native refuses function files as Unsupported |
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| Indirect addressing (`N7:[N7:0]`) | `ab_server` N-file, both transports (#646) - resolved by the driver, the transport sees the composed address |
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| T/C/R sub-elements (`.PRE`/`.ACC`/`.LEN`/`.POS`), 6-byte T/C/R element layout | **none** |
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### Native known gaps
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