Files
lmxopcua/tests/ZB.MOM.WW.OtOpcUa.Driver.Modbus.IntegrationTests/Pymodbus
Joseph Doherty b5464f11ee Phase 3 PR 50 -- DL260 bit-memory address helpers (Y/C/X/SP) + live coil integration tests. Adds four new static helpers to DirectLogicAddress covering every discrete-memory bank on the DL260: YOutputToCoil (Y0=coil 2048), CRelayToCoil (C0=coil 3072), XInputToDiscrete (X0=DI 0), SpecialToDiscrete (SP0=DI 1024). Each helper takes the DirectLOGIC ladder-logic address (e.g. 'Y0', 'Y17', 'C1777') and adds the octal-decoded offset to the bank's Modbus base per the DL260 user manual's I/O-configuration chapter table. Uses the same 'octal-walk + reject 8/9' pattern as UserVMemoryToPdu so misaligned addresses fail loudly with a clear ArgumentException rather than silently hitting the wrong coil. Fixes a pymodbus-config bug surfaced during integration-test validation: dl205.json had bits entries at cell indices 2048 / 3072 / 4000, but pymodbus's ModbusSimulatorContext.validate divides bit addresses by 16 before indexing into the shared cell array -- so Modbus coil 2048 reads cell 128, not cell 2048. The sim was returning Illegal Data Address (exception 02) for every bit read in the Y/C/scratch range. Moved bits entries to cells 128 (Y bank marker = 0b101 for Y0=ON, Y1=OFF, Y2=ON), 192 (C bank marker = 0b101 for C0/C1/C2), 250 (scratch cell covering coils 4000..4015). write list updated to the correct cell addresses. Unit tests: YOutputToCoil theory sweep (Y0->2048, Y1->2049, Y7->2055, Y10->2056 octal-to-decimal, Y17->2063, Y777->2559 top of DL260 Y range), CRelayToCoil theory (C0->3072 through C1777->4095), XInputToDiscrete theory, SpecialToDiscrete theory (with case-insensitive 'SP' prefix). Bit_address_rejects_non_octal_digits (Y8/C9/X18), Bit_address_rejects_empty, accepts_lowercase_prefix, accepts_bare_octal_without_prefix. 48/48 Modbus.Tests pass. Integration tests: DL205CoilMappingTests with three facts -- DL260_Y0_maps_to_coil_2048 (FC01 at Y0 returns ON), DL260_C0_maps_to_coil_3072 (FC01 at C0 returns ON), DL260_scratch_Crelay_supports_write_then_read (FC05 write + FC01 read round-trip at coil 4000 proves the DL-mapped coil bank is fully read/write capable end-to-end). 9/9 DL205 integration tests pass against the pymodbus dl205 profile with MODBUS_SIM_PROFILE=dl205. Caller opts into the helpers per tag the same way as PR 47's V-memory helper -- pass DirectLogicAddress.YOutputToCoil("Y0") as the ModbusTagDefinition Address; no driver-wide DL-family flag. PR 51 adds the X-input read-side integration test (there's nothing to write since X-inputs are FC02 discrete inputs, read-only); PR 52 exception-code translation; PR 53 transport reconnect-on-drop since DL260 doesn't send TCP keepalives.
2026-04-18 22:22:42 -04:00
..
Phase 3 PR 50 -- DL260 bit-memory address helpers (Y/C/X/SP) + live coil integration tests. Adds four new static helpers to DirectLogicAddress covering every discrete-memory bank on the DL260: YOutputToCoil (Y0=coil 2048), CRelayToCoil (C0=coil 3072), XInputToDiscrete (X0=DI 0), SpecialToDiscrete (SP0=DI 1024). Each helper takes the DirectLOGIC ladder-logic address (e.g. 'Y0', 'Y17', 'C1777') and adds the octal-decoded offset to the bank's Modbus base per the DL260 user manual's I/O-configuration chapter table. Uses the same 'octal-walk + reject 8/9' pattern as UserVMemoryToPdu so misaligned addresses fail loudly with a clear ArgumentException rather than silently hitting the wrong coil. Fixes a pymodbus-config bug surfaced during integration-test validation: dl205.json had bits entries at cell indices 2048 / 3072 / 4000, but pymodbus's ModbusSimulatorContext.validate divides bit addresses by 16 before indexing into the shared cell array -- so Modbus coil 2048 reads cell 128, not cell 2048. The sim was returning Illegal Data Address (exception 02) for every bit read in the Y/C/scratch range. Moved bits entries to cells 128 (Y bank marker = 0b101 for Y0=ON, Y1=OFF, Y2=ON), 192 (C bank marker = 0b101 for C0/C1/C2), 250 (scratch cell covering coils 4000..4015). write list updated to the correct cell addresses. Unit tests: YOutputToCoil theory sweep (Y0->2048, Y1->2049, Y7->2055, Y10->2056 octal-to-decimal, Y17->2063, Y777->2559 top of DL260 Y range), CRelayToCoil theory (C0->3072 through C1777->4095), XInputToDiscrete theory, SpecialToDiscrete theory (with case-insensitive 'SP' prefix). Bit_address_rejects_non_octal_digits (Y8/C9/X18), Bit_address_rejects_empty, accepts_lowercase_prefix, accepts_bare_octal_without_prefix. 48/48 Modbus.Tests pass. Integration tests: DL205CoilMappingTests with three facts -- DL260_Y0_maps_to_coil_2048 (FC01 at Y0 returns ON), DL260_C0_maps_to_coil_3072 (FC01 at C0 returns ON), DL260_scratch_Crelay_supports_write_then_read (FC05 write + FC01 read round-trip at coil 4000 proves the DL-mapped coil bank is fully read/write capable end-to-end). 9/9 DL205 integration tests pass against the pymodbus dl205 profile with MODBUS_SIM_PROFILE=dl205. Caller opts into the helpers per tag the same way as PR 47's V-memory helper -- pass DirectLogicAddress.YOutputToCoil("Y0") as the ModbusTagDefinition Address; no driver-wide DL-family flag. PR 51 adds the X-input read-side integration test (there's nothing to write since X-inputs are FC02 discrete inputs, read-only); PR 52 exception-code translation; PR 53 transport reconnect-on-drop since DL260 doesn't send TCP keepalives.
2026-04-18 22:22:42 -04:00

pymodbus simulator profiles

Two JSON-config profiles for pymodbus's ModbusSimulatorServer. Replaces the ModbusPal .xmpp profiles that lived here in PR 42 — pymodbus is headless, maintained, semantic about register layout, and pip-installable on Windows.

File What it simulates Test category
standard.json Generic Modbus TCP server — HR[0..31] = address-as-value, HR[100] declarative auto-increment via "action": "increment", alternating coils, scratch ranges for write tests. Trait=Standard
dl205.json AutomationDirect DirectLOGIC DL205 / DL260 quirks per docs/v2/dl205.md: low-byte-first string packing, CDAB Float32, BCD numerics, V-memory address markers, Y/C coil mappings. Inline _quirk comments per register name the behavior. Trait=DL205

Both bind TCP 5020 (pymodbus convention; sidesteps the Windows admin requirement for privileged port 502). The integration-test fixture (ModbusSimulatorFixture) defaults to localhost:5020 to match — override via MODBUS_SIM_ENDPOINT to point at a real PLC on its native port 502.

Run only one profile at a time (they share TCP 5020).

Install

pip install "pymodbus[simulator]==3.13.0"

The [simulator] extra pulls in aiohttp for the optional web UI / REST API. Pinned to 3.13.0 for reproducibility — avoid 4.x dev releases until stabilized. Requires Python ≥ 3.10. Windows Firewall will prompt on first bind; allow Private network.

Run

Foreground (Ctrl+C to stop). Use the serve.ps1 wrapper:

.\serve.ps1 -Profile standard
.\serve.ps1 -Profile dl205

Or invoke pymodbus directly:

pymodbus.simulator `
    --modbus_server srv `
    --modbus_device dev `
    --json_file .\standard.json `
    --http_port 8080

Web UI at http://localhost:8080 lets you inspect + poke registers manually. Pass --no_http (or -HttpPort 0 to serve.ps1) to disable.

Run the integration tests

In a separate shell, with the simulator running:

cd C:\Users\dohertj2\Desktop\lmxopcua
dotnet test tests\ZB.MOM.WW.OtOpcUa.Driver.Modbus.IntegrationTests

Tests auto-skip with a clear SkipReason if localhost:5020 isn't reachable within 2 seconds. Filter by trait when both profiles' tests coexist:

dotnet test ... --filter "Trait=Standard"
dotnet test ... --filter "Trait=DL205"

What's encoded in each profile

standard.json

  • HR[0..31]: each register's value equals its address. Easy mental map.
  • HR[100]: "action": "increment" ticks 0..65535 on every register access — drives subscribe-and-receive tests so they have a register that changes without a write.
  • HR[200..209]: scratch range for write-roundtrip tests.
  • Coils[0..31]: alternating on/off (even=on).
  • Coils[100..109]: scratch.
  • All addresses 0..1023 are writable ("write": [[0, 1023]]).

dl205.json (per docs/v2/dl205.md)

HR address Quirk demonstrated Raw value Decoded
0 (V0) Register 0 is valid (rejects-register-0 rumour disproved) 51966 (0xCAFE) marker
1024 (V2000 octal) V-memory octal-to-decimal mapping 8192 (0x2000) marker
8448 (V40400 octal) V40400 → PDU 0x2100 (NOT register 0) 16448 (0x4040) marker
1040..1042 String "Hello" packed first-char-low-byte 25928, 27756, 111 "Hello"
1056..1057 Float32 1.5f in CDAB word order 0, 16320 1.5f
1072 Decimal 1234 in BCD encoding 4660 (0x1234) 1234
1280..1407 128-register block (FC03 cap = 128 above spec's 125) first/last/mid markers; rest defaults to 0 for FC03 cap test
Coil address Quirk demonstrated
2048 Y0 maps to coil 2048 (DL260 layout)
3072 C0 maps to coil 3072 (DL260 layout)
4000..4007 Scratch C-relay range for write-roundtrip tests

The DL260 X-input markers (FC02 discrete inputs) are not encoded separately because the profile uses shared blocks: true (matches DL series memory model) — coils/DI/HR/IR overlay the same word address space. Tests that target FC02 against this profile end up reading the same bit positions as the coils they share with.

What's IN pymodbus that wasn't in ModbusPal

  • All four standard tables (HR, IR, coils, DI) configurable via co size / di size / hr size / ir size setup keys.
  • Per-register raw uint16 seeding{"addr": 1040, "value": 25928} puts exactly that 16-bit value on the wire. No interpretation.
  • Built-in actions: increment, random, timestamp, reset, uptime for declarative dynamic registers. No Python script alongside the config required.
  • Custom actions — point --custom_actions_module at a .py file exposing callables to express anything more complex (per-second wall-clock ticks, BCD synthesis, etc.).
  • Headless — pure CLI process, no Java, no Swing. Pip-installable. Plays well with CI runners.
  • Web UI / REST API--http_port 8080 adds an aiohttp server for live inspection. Optional.
  • Maintained — current stable 3.13.0 (April 2026), active development on 4.0 dev branch.

Trade-offs vs the hand-authored ModbusPal profiles

  • pymodbus's built-in float32 type stores in pymodbus's word order; for explicit DL205 CDAB control we seed two raw uint16 entries instead. Documented inline in dl205.json.
  • increment action ticks per-access, not wall-clock. A 250ms-poll integration test sees variation either way; for strict 1Hz cadence add --custom_actions_module my_actions.py with a time.time()-based callable.
  • dl205.json uses shared blocks: true because it matches DL series memory model; standard.json uses shared blocks: false so coils and HR address spaces are independent (more like a textbook PLC).

File format reference

{
  "server_list": {
    "<server-name>": {
      "comm": "tcp",
      "host": "0.0.0.0",
      "port": 5020,
      "framer": "socket",
      "device_id": 1
    }
  },
  "device_list": {
    "<device-name>": {
      "setup": {
        "co size": N, "di size": N, "hr size": N, "ir size": N,
        "shared blocks": false,
        "type exception": false,
        "defaults": { "value": {...}, "action": {...} }
      },
      "invalid": [],
      "write": [[<from>, <to>]],
      "bits":    [{"addr": N, "value": 0|1}],
      "uint16":  [{"addr": N, "value": <0..65535>, "action"?: "increment", "parameters"?: {...}}],
      "uint32":  [{"addr": N, "value": <int>}],
      "float32": [{"addr": N, "value": <float>}],
      "string":  [{"addr": N, "value": "<text>"}],
      "repeat":  []
    }
  }
}

The CLI args --modbus_server <server-name> --modbus_device <device-name> pick which entries the simulator binds.

References