Phase 3 PR 50 -- DL260 bit-memory address helpers (Y/C/X/SP) + live coil integration tests. Adds four new static helpers to DirectLogicAddress covering every discrete-memory bank on the DL260: YOutputToCoil (Y0=coil 2048), CRelayToCoil (C0=coil 3072), XInputToDiscrete (X0=DI 0), SpecialToDiscrete (SP0=DI 1024). Each helper takes the DirectLOGIC ladder-logic address (e.g. 'Y0', 'Y17', 'C1777') and adds the octal-decoded offset to the bank's Modbus base per the DL260 user manual's I/O-configuration chapter table. Uses the same 'octal-walk + reject 8/9' pattern as UserVMemoryToPdu so misaligned addresses fail loudly with a clear ArgumentException rather than silently hitting the wrong coil. Fixes a pymodbus-config bug surfaced during integration-test validation: dl205.json had bits entries at cell indices 2048 / 3072 / 4000, but pymodbus's ModbusSimulatorContext.validate divides bit addresses by 16 before indexing into the shared cell array -- so Modbus coil 2048 reads cell 128, not cell 2048. The sim was returning Illegal Data Address (exception 02) for every bit read in the Y/C/scratch range. Moved bits entries to cells 128 (Y bank marker = 0b101 for Y0=ON, Y1=OFF, Y2=ON), 192 (C bank marker = 0b101 for C0/C1/C2), 250 (scratch cell covering coils 4000..4015). write list updated to the correct cell addresses. Unit tests: YOutputToCoil theory sweep (Y0->2048, Y1->2049, Y7->2055, Y10->2056 octal-to-decimal, Y17->2063, Y777->2559 top of DL260 Y range), CRelayToCoil theory (C0->3072 through C1777->4095), XInputToDiscrete theory, SpecialToDiscrete theory (with case-insensitive 'SP' prefix). Bit_address_rejects_non_octal_digits (Y8/C9/X18), Bit_address_rejects_empty, accepts_lowercase_prefix, accepts_bare_octal_without_prefix. 48/48 Modbus.Tests pass. Integration tests: DL205CoilMappingTests with three facts -- DL260_Y0_maps_to_coil_2048 (FC01 at Y0 returns ON), DL260_C0_maps_to_coil_3072 (FC01 at C0 returns ON), DL260_scratch_Crelay_supports_write_then_read (FC05 write + FC01 read round-trip at coil 4000 proves the DL-mapped coil bank is fully read/write capable end-to-end). 9/9 DL205 integration tests pass against the pymodbus dl205 profile with MODBUS_SIM_PROFILE=dl205. Caller opts into the helpers per tag the same way as PR 47's V-memory helper -- pass DirectLogicAddress.YOutputToCoil("Y0") as the ModbusTagDefinition Address; no driver-wide DL-family flag. PR 51 adds the X-input read-side integration test (there's nothing to write since X-inputs are FC02 discrete inputs, read-only); PR 52 exception-code translation; PR 53 transport reconnect-on-drop since DL260 doesn't send TCP keepalives.
This commit is contained in:
Joseph Doherty
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using Shouldly;
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using Xunit;
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namespace ZB.MOM.WW.OtOpcUa.Driver.Modbus.IntegrationTests.DL205;
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/// <summary>
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/// Verifies DL260 I/O-memory coil mappings against the <c>dl205.json</c> pymodbus profile.
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/// DirectLOGIC Y-outputs and C-relays are exposed to Modbus as FC01/FC05 coils, but at
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/// non-zero base addresses that confuse operators used to "Y0 is the first coil". The sim
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/// seeds Y0 → coil 2048 = ON and C0 → coil 3072 = ON as fixed markers.
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/// </summary>
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[Collection(ModbusSimulatorCollection.Name)]
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[Trait("Category", "Integration")]
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[Trait("Device", "DL205")]
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public sealed class DL205CoilMappingTests(ModbusSimulatorFixture sim)
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{
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[Fact]
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public async Task DL260_Y0_maps_to_coil_2048()
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{
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if (sim.SkipReason is not null) Assert.Skip(sim.SkipReason);
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if (!string.Equals(Environment.GetEnvironmentVariable("MODBUS_SIM_PROFILE"), "dl205",
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StringComparison.OrdinalIgnoreCase))
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{
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Assert.Skip("MODBUS_SIM_PROFILE != dl205 — skipping.");
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}
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var coil = DirectLogicAddress.YOutputToCoil("Y0");
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coil.ShouldBe((ushort)2048);
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var options = BuildOptions(sim, [
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new ModbusTagDefinition("DL260_Y0",
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ModbusRegion.Coils, Address: coil,
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DataType: ModbusDataType.Bool, Writable: false),
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]);
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await using var driver = new ModbusDriver(options, driverInstanceId: "dl205-y0");
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await driver.InitializeAsync("{}", TestContext.Current.CancellationToken);
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var results = await driver.ReadAsync(["DL260_Y0"], TestContext.Current.CancellationToken);
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results[0].StatusCode.ShouldBe(0u);
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results[0].Value.ShouldBe(true, "dl205.json seeds coil 2048 (Y0) = ON");
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}
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[Fact]
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public async Task DL260_C0_maps_to_coil_3072()
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{
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if (sim.SkipReason is not null) Assert.Skip(sim.SkipReason);
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if (!string.Equals(Environment.GetEnvironmentVariable("MODBUS_SIM_PROFILE"), "dl205",
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StringComparison.OrdinalIgnoreCase))
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{
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Assert.Skip("MODBUS_SIM_PROFILE != dl205 — skipping.");
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}
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var coil = DirectLogicAddress.CRelayToCoil("C0");
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coil.ShouldBe((ushort)3072);
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var options = BuildOptions(sim, [
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new ModbusTagDefinition("DL260_C0",
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ModbusRegion.Coils, Address: coil,
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DataType: ModbusDataType.Bool, Writable: false),
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]);
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await using var driver = new ModbusDriver(options, driverInstanceId: "dl205-c0");
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await driver.InitializeAsync("{}", TestContext.Current.CancellationToken);
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var results = await driver.ReadAsync(["DL260_C0"], TestContext.Current.CancellationToken);
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results[0].StatusCode.ShouldBe(0u);
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results[0].Value.ShouldBe(true, "dl205.json seeds coil 3072 (C0) = ON");
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}
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[Fact]
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public async Task DL260_scratch_Crelay_supports_write_then_read()
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{
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if (sim.SkipReason is not null) Assert.Skip(sim.SkipReason);
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if (!string.Equals(Environment.GetEnvironmentVariable("MODBUS_SIM_PROFILE"), "dl205",
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StringComparison.OrdinalIgnoreCase))
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{
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Assert.Skip("MODBUS_SIM_PROFILE != dl205 — skipping.");
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}
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// Scratch C-relay at coil 4000 (per dl205.json _quirk note) is writable. Write=true then
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// read back to confirm FC05 round-trip works against the DL-mapped coil bank.
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var options = BuildOptions(sim, [
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new ModbusTagDefinition("DL260_C_Scratch",
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ModbusRegion.Coils, Address: 4000,
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DataType: ModbusDataType.Bool, Writable: true),
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]);
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await using var driver = new ModbusDriver(options, driverInstanceId: "dl205-cscratch");
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await driver.InitializeAsync("{}", TestContext.Current.CancellationToken);
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var writeResults = await driver.WriteAsync(
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[new(FullReference: "DL260_C_Scratch", Value: true)],
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TestContext.Current.CancellationToken);
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writeResults[0].StatusCode.ShouldBe(0u);
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var readResults = await driver.ReadAsync(["DL260_C_Scratch"], TestContext.Current.CancellationToken);
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readResults[0].StatusCode.ShouldBe(0u);
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readResults[0].Value.ShouldBe(true);
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}
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private static ModbusDriverOptions BuildOptions(ModbusSimulatorFixture sim, IReadOnlyList<ModbusTagDefinition> tags)
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=> new()
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{
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Host = sim.Host,
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Port = sim.Port,
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UnitId = 1,
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Timeout = TimeSpan.FromSeconds(2),
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Tags = tags,
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Probe = new ModbusProbeOptions { Enabled = false },
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};
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}
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@@ -36,9 +36,9 @@
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[1280, 1282],
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[1343, 1343],
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[1407, 1407],
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[2048, 2050],
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[3072, 3074],
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[4000, 4007],
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[128, 128],
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[192, 192],
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[250, 250],
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[8448, 8448]
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],
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@@ -88,25 +88,14 @@
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],
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"bits": [
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{"_quirk": "Y0 marker. DL260 maps Y0 to coil 2048 (0-based). Coil 2048 = ON proves the mapping.",
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"addr": 2048, "value": 1},
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{"addr": 2049, "value": 0},
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{"addr": 2050, "value": 1},
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{"_quirk": "Y-output bank marker cell. pymodbus's simulator maps Modbus FC01/02/05 bit-addresses to cell index = bit_addr / 16; so Modbus coil 2048 lives at cell 128 bit 0. Y0=ON (bit 0), Y1=OFF (bit 1), Y2=ON (bit 2) -> value=0b00000101=5 proves DL260 mapping Y0 -> coil 2048.",
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"addr": 128, "value": 5},
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{"_quirk": "C0 marker. DL260 maps C0 to coil 3072 (0-based). Coil 3072 = ON proves the mapping.",
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"addr": 3072, "value": 1},
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{"addr": 3073, "value": 0},
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{"addr": 3074, "value": 1},
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{"_quirk": "C-relay bank marker cell. Modbus coil 3072 -> cell 192 bit 0. C0=ON (bit 0), C1=OFF (bit 1), C2=ON (bit 2) -> value=5 proves DL260 mapping C0 -> coil 3072.",
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"addr": 192, "value": 5},
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{"_quirk": "Scratch C-relays for write-roundtrip tests against the writable C range.",
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"addr": 4000, "value": 0},
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{"addr": 4001, "value": 0},
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{"addr": 4002, "value": 0},
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{"addr": 4003, "value": 0},
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{"addr": 4004, "value": 0},
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{"addr": 4005, "value": 0},
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{"addr": 4006, "value": 0},
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{"addr": 4007, "value": 0}
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{"_quirk": "Scratch cell for coil 4000..4015 write round-trip tests. Cell 250 holds Modbus coils 4000-4015; all bits start at 0 and tests set specific bits via FC05.",
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"addr": 250, "value": 0}
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],
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"uint32": [],
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