chore: organize solution into module folders (Core/Server/Drivers/Client/Tooling)
Group all 69 projects into category subfolders under src/ and tests/ so the Rider Solution Explorer mirrors the module structure. Folders: Core, Server, Drivers (with a nested Driver CLIs subfolder), Client, Tooling. - Move every project folder on disk with git mv (history preserved as renames). - Recompute relative paths in 57 .csproj files: cross-category ProjectReferences, the lib/ HintPath+None refs in Driver.Historian.Wonderware, and the external mxaccessgw refs in Driver.Galaxy and its test project. - Rebuild ZB.MOM.WW.OtOpcUa.slnx with nested solution folders. - Re-prefix project paths in functional scripts (e2e, compliance, smoke SQL, integration, install). Build green (0 errors); unit tests pass. Docs left for a separate pass. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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using Shouldly;
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using Xunit;
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namespace ZB.MOM.WW.OtOpcUa.Driver.Modbus.IntegrationTests.DL205;
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/// <summary>
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/// Verifies the DL260 X-input discrete-input mapping against the <c>dl205.json</c>
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/// pymodbus profile. X-inputs are FC02 discrete-input-only (Modbus doesn't allow writes
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/// to discrete inputs), and the DirectLOGIC convention is X0 → DI 0 with octal offsets
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/// for subsequent addresses. The sim seeds X20 octal (= DI 16) = ON so the test can
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/// prove the helper routes through to the right cell.
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/// </summary>
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/// <remarks>
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/// X0 / X1 / …X17 octal all share cell 0 (DI 0-15 → cell 0 bits 0-15) which conflicts
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/// with the V0 uint16 marker; we can't seed both types at cell 0 under shared-blocks
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/// semantics. So the test uses X20 octal (first address beyond the cell-0 boundary) which
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/// lands cleanly at cell 1 bit 0 and leaves the V0 register-zero quirk intact.
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/// </remarks>
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[Collection(ModbusSimulatorCollection.Name)]
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[Trait("Category", "Integration")]
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[Trait("Device", "DL205")]
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public sealed class DL205XInputTests(ModbusSimulatorFixture sim)
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{
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[Fact]
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public async Task DL260_X20_octal_maps_to_DiscreteInput_16_and_reads_ON()
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{
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if (sim.SkipReason is not null) Assert.Skip(sim.SkipReason);
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if (!string.Equals(Environment.GetEnvironmentVariable("MODBUS_SIM_PROFILE"), "dl205",
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StringComparison.OrdinalIgnoreCase))
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{
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Assert.Skip("MODBUS_SIM_PROFILE != dl205 — skipping.");
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}
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// X20 octal = decimal 16 = DI 16 per the DL260 convention (X-inputs start at DI 0).
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var di = DirectLogicAddress.XInputToDiscrete("X20");
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di.ShouldBe((ushort)16);
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var options = BuildOptions(sim, [
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new ModbusTagDefinition("DL260_X20",
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ModbusRegion.DiscreteInputs, Address: di,
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DataType: ModbusDataType.Bool, Writable: false),
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// Unpopulated-X control: pymodbus returns 0 (not exception) for any bit in the
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// configured DI range that wasn't explicitly seeded — per docs/v2/dl205.md
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// "Reading a non-populated X input ... returns zero, not an exception".
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new ModbusTagDefinition("DL260_X21_off",
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ModbusRegion.DiscreteInputs, Address: DirectLogicAddress.XInputToDiscrete("X21"),
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DataType: ModbusDataType.Bool, Writable: false),
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]);
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await using var driver = new ModbusDriver(options, driverInstanceId: "dl205-xinput");
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await driver.InitializeAsync("{}", TestContext.Current.CancellationToken);
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var results = await driver.ReadAsync(["DL260_X20", "DL260_X21_off"], TestContext.Current.CancellationToken);
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results[0].StatusCode.ShouldBe(0u);
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results[0].Value.ShouldBe(true, "dl205.json seeds cell 1 bit 0 (X20 octal = DI 16) = ON");
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results[1].StatusCode.ShouldBe(0u, "unpopulated X inputs must read cleanly — DL260 does NOT raise an exception");
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results[1].Value.ShouldBe(false);
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}
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private static ModbusDriverOptions BuildOptions(ModbusSimulatorFixture sim, IReadOnlyList<ModbusTagDefinition> tags)
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=> new()
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{
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Host = sim.Host,
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Port = sim.Port,
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UnitId = 1,
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Timeout = TimeSpan.FromSeconds(2),
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Tags = tags,
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Probe = new ModbusProbeOptions { Enabled = false },
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};
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}
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